1. Technical Field
The present disclosure relates to the field of integrated circuit design. The present disclosure relates more particularly to formation of strain inducing structures in a transistor.
2. Description of the Related Art
Integrated circuits generally include many transistors formed at the surface of a semiconductor substrate. Since the advent of integrated circuits, there has been a continuous scaling of transistor size to enable putting more transistors in a smaller area of the semiconductor substrate. This scaling has allowed integrated circuits to contain more complex circuits in a same area and thus decrease cost. Additionally, as transistors decrease in size, the switching speed increases, thus improving performance.
However, as the size of transistors has continued to shrink, so has the distance separating transistors from one another. This shrinking of the separation distance has produced undesired effects in transistor performance. In particular electric fields generated in one transistor more readily affect the performance of an adjacent transistor. This effect can degrade the performance of individual transistors and on a large scale can affect the performance of the integrated circuit as a whole. Additionally, leakage currents develop between adjacent transistors, affecting performance and using power. This extra power usage is uneconomical and also can heat the chip, further adversely affecting the chip.
To reduce these leakage currents, field oxide regions have been placed between transistor regions. At one time the field oxide regions were a barrier of silicon oxide with a portion above and a portion below the surface of the substrate formed by local oxidation of silicon (LOCOS).
But as transistor size has further shrunk, other techniques for isolating adjacent transistors have arisen. In particular, shallow trench isolation (STI) has been utilized to isolate adjacent transistors from each other. In STI processing, a portion of the silicon substrate between adjacent transistors is etched to form a trench in the substrate. The trench is then filled with a dielectric material which serves to inhibit leakage currents between the adjacent transistors.
Scaling of transistor size has served to improve switching speed (the maximum speed at which a transistor can be switched off or on), conduction properties, and circuit density. However as CMOS technology has reached the 32 nm and 16 nm nodes, scaling has become more difficult and new techniques for improving device function have been sought.
One technique for improving transistor properties is to introduce strain on the channel of the transistor. This has been done in the past by carefully forming strain inducing layers of materials in the substrate near the channel, and also overlying the gate electrode of the transistor. The strain inducing layers induce either a tensile or compressive strain on the channel region of the transistor, according to the type of the transistor, and in so doing improve carrier mobility in the channel region. The improved carrier mobility enhances current conduction in the channel region, which in turn allows for lower power dissipation and enhanced transconductance. The enhanced transconductance means that a larger current can be induced in the channel with a smaller gate to source voltage, allowing for lower supply voltages to be used on chip. The lower supply voltages allow for further reduction of power dissipation.
FIG. 1 is a cross section of a conventional strained transistor 20. The transistor is formed in a monocrystalline semiconductor substrate 22. Lightly doped source and drain regions 24 are formed in the monocrystalline semiconductor substrate 22. Heavily doped source and drain regions 26 are also formed in the monocrystalline semiconductor substrate 22. A transistor channel region 27 is positioned in the monocrystalline semiconductor substrate 22 between the lightly doped source and drain regions 24. A gate oxide 28 is on the surface of the monocrystalline semiconductor substrate 22 overlying the channel region 27. A gate electrode 30 having vertical sidewalls is positioned on the gate oxide 28. Sidewall spacers 32 are positioned adjacent the vertical sidewalls of the gate electrode 30.
A strain inducing dielectric layer 34 is deposited overlying the gate electrode 30, the sidewall spacers 32, and the source/drain regions 26. For an N-type transistor, the strain inducing layer 34 is a silicon nitride layer having a compressive stress. For a P-type transistor the strain inducing layer 34 is a silicon nitride layer having a tensile stress. The strain inducing layer 34 can be deposited having the desired magnitude of compressive stress or tensile stress as is known in the art in order to achieve some level of stress within the channel region 27.
Force arrows are drawn in the strain inducing layer 34 to show one of the directions of stress in the various parts of the strain inducing layer 34. For horizontal portions of the stress inducing layer 34, there is compressive or tensile stress is in the horizontal direction. (There may be compressive stress in other directions, but for purposes of this study, these directions are of the most interest.) For the portions of the stress inducing layer 34 formed over the sidewall spacers 32, the stress is primarily in the vertical direction, with a small horizontal component.